Description

VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.

Readership

Hardware Verification Engineers using VHDL

Contents

1 Fundamental Concepts
2 Scalar Data Types and Operations
3 Sequential Statements
4 Composite Data Types and Operations
5 Basic Modeling Constructs
6 Case Study: A Pipelined Complex Multiplier Accumulator
7 Subprograms
8 Packages and Use Clauses
9 Aliases
10 External Names in Testbenches
11 Properties and Assertion-Based Design
12 Resolved Signals
13 Generics
14 Components and Configurations
15 Generate Statements
16 Access Types and Abstract Data Types
17 Files and Input/Output
18 Case Study: Queuing Networks
19 Attributes and Groups
20 Design for Synthesis
21 Case Study: System Design using the Gumnut Core
22 Miscellaneous Topics
A Standard Packages
B Related Standards
C VHDL Syntax
D Differences Among VHDL Versions
E Answers to Exercises
References
Index

Author Information

By Peter J. Ashenden, Adjunct Associate Professor, School of Computer Science, University of Adelaide, Australia